Cache coherency in multiple bus systems

The cache coherency problem in a multiprocessor system has received increasing attention in recent years. The major motive behind such interest is the availability of commercial multiprocessor systems, e.g. Encore's Multimax and Sequent's Balance and Symmetry series. A number of cache coherency protocols have been reported in the literature, the most popular protocols being the snooping protocols. These assume a single-bus system where all the caches snoop on the bus in order to update their contents to ensure data consistency. An extension of snooping protocols for multiprocessor systems with multiple bus networks was made. It was created by utilizing a cache coherency bus (CCB) in addition to the data buses of the network. The CCB was then used for cache coherency communication between the processing elements and cache-to-cache transfer between the caches. In addition, the data buses were used for the memory-to-cache transfers. Five known protocols were examined (three invalidation protocols and two broadcast protocols), in addition to two protocols proposed by the study (one invalidation protocol and one broadcast protocol). A simulation model was used to compare between these protocols. © 1992 Tayor and Francis Ltd. © 2015 Elsevier B.V., All rights reserved.